Are there any FPGA/ASIC design engineers out there? I'm working on a pipelined arithmetic design for an Altera FPGA. I figured it would be a good idea to clock every flip flop in the module with the same edge of the same clock. So when data changes at the output of flip flop A the rising edge of clock edge N it's not clocked into flip flop B until rising edge N+1 because of the propagation delay. This is exactly what I want, but since every flip flop in the pipeline is clocked by the same edge of the same clock, the data changes very close to the same clock edge that clocks it into the next flip flop. Is it typical to implement pipelines in this manner, using the same edge of the same clock for every flip flop, or is it practical to use the rising edge of the clock to latch in data from the stage which changes on the falling edge?